The present invention relates to a semiconductor device and a semiconductor chip mounting substrate. More particularly, the present invention relates to a flip chip mounting substrate, wherein an area between a semiconductor chip and the flip chip mounting substrate, under the semiconductor chip, is filled with resin. The present invention also relates to a flip chip mounting structure.
In recent years, semiconductor devices have been increasingly incorporated within a variety of electronic devices. The electronic devices have demonstrated a corresponding increase in reliability, thereby enhancing the need for incorporation of semiconductor devices in a number of products.
In general, a semiconductor device has a structure in which a semiconductor chip is mounted on a substrate. Along with a reduction in size and packing density of semiconductor chips, a flip chip mounting method has been introduced in which projected electrodes are used in conjunction with a semiconductor chip to mount the semiconductor chip on the surface of the substrate.
FIGS. 10 through 13 are related to the present invention and illustrate a flip chip mounting substrate which lays a foundation for the present invention. FIGS. 10 through 13 illustrate a flip chip mounting substrate 100 and a mounting structure for mounting a surface mounting element on the flip chip mounting substrate 100. Semiconductor chip 102 is considered as an example for use with flip chip mounting substrate 100.
FIGS. 10 through 13 are related, with FIG. 10 illustrating a side sectional view of semiconductor chip 102 mounted on flip chip mounting substrate 100; FIG. 11 illustrating a side sectional view of an under-fill resin 118 formed with semiconductor chip 102 of FIG. 10; FIG. 12 illustrating an exploded perspective view of flip chip mounting substrate 100; and FIG. 13 illustrating a plan view of flip chip mounting substrate 100. According to the following explanation, flip chip mounting substrate 100 is applied to a semiconductor device having a Ball Grid Array ("BGA") structure.
As illustrated in FIG. 10, mounting substrate 100 includes a substrate body 106 and a solder resist 110. The substrate body 106 is, for example, a multilayer printed wiring board. A bump for external connection 114 (see FIG. 12) is formed at a lower surface of substrate body 106 and a pad 109 is formed at an upper surface of substrate body 106. Pad 109 and the external connection bump 114 are connected through a wiring layer 108 and an interlayer wiring (not illustrated) which is formed in substrate body 106.
Solder resist 110, which is an insulation film formed of an insulation resin, is disposed on flip chip mounting substrate 100. Solder resist 110 prevents incorrect mounting of semiconductor chip 102 and pad 109 at an area other than a predetermined connecting position.
As illustrated in FIG. 10, solder resist 110 is provided with a rectangular aperture 112 at a position corresponding to gold bump 104. The gold bump 104 is formed on semiconductor chip 102.
As illustrated in FIG. 12, each rectangular aperture 112 is not continuous and is therefore independent of other rectangular apertures. As illustrated, gold bump 104 may be part of a group of bumps 104 for placement within corresponding rectangular apertures 112. In more practical terms, a corner portion 122, which is formed as a part of solder resist 110, is provided between the adjacent apertures 112, and thereby each aperture 112 is respectively independent. Moreover, the forming position of aperture 112 has been set at an internal side of a predetermined external circumference 113 (a position indicated by a broken line in FIG. 12) of semiconductor chip 102, when the semiconductor chip 102 is mounted to mounting substrate 100. Gold bump 104, explained above, is arranged at a peripheral area of semiconductor chip 102.
The junction position of gold bump 104 with pad 109 is exposed by forming aperture 112 in solder resist 110. Thus, gold bump 104 and pad 109 can be electrically connected.
As illustrated in FIGS. 10 and 11, gold bump 104 is joined by solder 116 on pad 109 when semiconductor chip 102 is mounted to mounting substrate 100. As illustrated in FIG. 11, under-fill resin 118 is applied to an area between semiconductor chip 102 and mounting substrate 100. This under-fill resin 118 is provided to ease stress which is generated by a difference in thermal expansion between semiconductor chip 102 and flip chip mounting substrate 100, and to protect a joining area between gold bump 104 and pad 109.
This under-fill resin 118 is provided between semiconductor chip 102 and mounting substrate 100 after the semiconductor chip 102 is joined to pad 109 using solder 116.
In more practical terms, under-fill resin 118 is a fluid which is supplied to an area between semiconductor chip 102 and mounting substrate 100 before hardening. Thereafter, under-fill resin 118 is hardened by heat treatment.
Aperture 112, within solder resist 110, is preferably formed to pad 109 from the viewpoint of the function. However, when the pitch of gold bump 104 becomes as narrow as 200 m, due to an increase in a number of pins of semiconductor chip 102, it is difficult to form a corresponding aperture within solder resist 110.
Therefore, aperture 112 is formed for every line of gold bump 104 at one side of semiconductor chip 102, and aperture 112 is formed in a rectangular shape. Accordingly, four apertures are formed in a rectangular shape because the gold bump 104 is peripherally arranged as a plurality of gold bumps 104, as illustrated in FIG. 12.
However, when semiconductor chip 102 is mounted using the mounting substrate 100 of the existing structure explained above, there arises a problem in that void 120 (see FIG. 11) is generated in under-fill resin 118, provided between the semiconductor chip 102 and mounting substrate 100.
When void 120 is generated in under-fill resin 118, as explained above, solder 116 flows into void 120, resulting in the probability of a short-circuit to an adjacent gold bump 104. Moreover, when under-fill resin 118 is heated, water content in void 120 is expanded. This results in a potential that a crack may be generated in under-fill resin 118 or a connection between the gold bump 104 and pad 109 may be broken.
As set forth below, the inventors of the present invention have discovered a reason why the void is generated in the under-fill resin 118 when mounting substrate 100 of the structure of the related art is used.
FIG. 14 through FIG. 16 illustrate a change of conditions with respect to time where a fluid form of under-fill resin 118 is supplied to an area between semiconductor chip 102 and mounting substrate 100. Each figure respectively illustrates enlargement of a corner part of the mounting substrate. Under-fill resin 118 is supplied toward a lower direction from an upper side of each figure.
The inventors of the present invention have conducted an experiment to determine how the flow of under-fill resin 118 varies with respect to time by supplying under-fill resin 118 to an area between semiconductor chip 102 and mounting substrate 100.
As a result, it has been proven that a flowing rate of under-fill resin 118 on the mounting substrate 100 is different depending on a place of application, as illustrated in FIG. 14. Namely, it has been proven that a first flow rate (indicated by the arrow V1 in FIG. 14) of under-fill resin 118 on the solder resist is high, while a second flow rate (indicated by the arrow V2 in FIG. 14) in aperture 112 is low.
There are essentially two reasons for a higher flow rate of under-fill resin 118 on solder resist 110. First, the solder resist 110 is also a resin (like the under-fill resin 118) and therefore has good wettability, and second, since the upper surface of the solder resist 110 is formed as a smooth surface, flow of the under-fill resin 118 is not restricted by many factors.
Meanwhile, under-fill resin 118 in the aperture 112 is thought to flow at a lower rate V2 because of the following reasons. One reason is that since the projected and recessed areas are formed on pad 109 within the aperture 112, these projected and recessed areas interfere with flow of the under-fill resin 118. Another reason is that since the space of the aperture 112 is larger than the upper part of the solder resist 110, an effect of capillarity is lowered and friction for interfering flow of the under-fill resin 118 becomes large.
As explained above, when the flow rate V1 of the under-fill resin 118 on the solder resist 110 is higher than the flow rate V2 of the under-fill resin 118 within the aperture 112, the under-fill resin 118 flowing on the solder resist 110 at the higher flow rate V1 generates a secondary flow (this flow is indicated by the arrows A in FIG. 15) to turn around the aperture 112 in an area near an end part of aperture 112.
However, since the under-fill resin 118 flows at a lower rate in the aperture 112 as explained above, a space (i.e. void) is generated in a forming part of the aperture 112 (particularly at the end part of the aperture 112). In this case, according to the related art, since the forming position of aperture 112 has been set at a more internal side than a external circumference position, indicated by broken line 113, in the mounting condition, an escaping route of this void is closed by the under-fill resin 118 flowing from an external side position of the aperture 112 and thereby the position of the space (void) is formed on the aperture 112.
Moreover, when the under-fill resin 118 further flows, the under-fill resin 118 exists continuously in the area leaving a space as illustrated in FIG. 16, and thereby void 120 is formed on the aperture.